1. Field of the Invention
The present invention relates generally to semiconductor wafer cleaning and, more particularly, to post chemical mechanical polishing (CMP) copper cleaning.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform chemical mechanical polishing (CMP) operations and wafer cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material grows. Without planarization, fabrication of further metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then, metal CMP operations are performed to remove excess metallization. After any such CMP operation, it is necessary that the planarized wafer be cleaned to remove particulates and contaminants.
FIG. 1A shows a cross-sectional view of a wafer having a copper layer 104 deposited over the top surface of the wafer. An oxide layer 100 is deposited over a semiconductor substrate (not shown). Well-known photolithography and etching techniques may be used to form patterned features in the oxide layer 100. Next, the top surface of the wafer is coated with a copper layer 104 and the patterned features are thereby filled with copper to form copper lines 102.
FIG. 1B shows a cross-sectional view of the wafer of FIG. 1A after the top surface has undergone a chemical mechanical polishing (CMP) operation. The top surface is polished until the top surface is planar and the oxide layer 100 is exposed.
Unfortunately, the CMP operation is likely to leave imperfections on the surface of the wafer. For example, the CMP operation may leave micro-scratches on the surface of the copper metallization features and on the surface of the silicon dioxide layer. These micro-scratches are likely to contain embedded slurry and trace amounts of copper material on the silicon dioxide layer from the CMP operation. FIG. 1B demonstrates how the CMP operation leaves a rough copper oxide layer 110 over the top surface of the copper line 102. It is believed that the roughness in the copper oxide layer is primarily due to copper from the metallization features that is left on the surface of the wafer after the CMP operation.
FIG. 1C shows a cross-sectional view of the wafer of FIG. 1B after a metal via has been formed to make contact with the copper line 102. A second oxide layer 101 is deposited over the polished top surface of the wafer. Well-known photolithography and etching techniques may be used to form conductive vias 122. The vias are filled with a barrier layer 120, such as tantalum nitride (TaN), which provides adhesion between the conductive via 122 and the copper line 102.
Unfortunately, the rough copper oxide layer 110 caused by the CMP operation may cause processing flaws. The damaged wafer surface, for example, may result in vias that form inadequate bonds to metallization features. In other words, the rough copper oxide layer 110 creates adhesion problems at the contact area between the conductive via 122 and the copper line 102. The adhesive strength at the contact area is diminished where the left over copper from the CMP operations interferes with the adhesive bond between the barrier layer 120 and the copper line 102. Thus, the barrier layer 120 will not form an adequately adhesive bond with the copper line 102.
Another fabrication problem created by a typical CMP operation is faulty electrical connections between vias 122 and copper lines 102 caused by the rough copper oxide layer 110. For instance, the rough copper layer 110 may increase the resistance of the connection between the copper lines 102 and the conductive vias 122 to an unacceptably high level. A resistance that is too high for one via connection will cause an entire semiconductor device to be inoperable or produce slower devices. As can be appreciated, the fabrication process becomes very costly when a multitude of devices must be discarded due to faulty electrical connections between vias and copper lines.
In view of the foregoing, there is a need for a cleaning process that avoids the problems of the prior art by implementing wafer cleaning and associated fabrication techniques that provide for better connections between copper lines and conductive vias.
Broadly speaking, the present invention fills these needs by providing a method for cleaning and treating a wafer after a chemical mechanical polishing (CMP) operation. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method is provided for cleaning a surface of a semiconductor wafer after a CMP operation. An improved cleaning chemical (ICC) is applied to the surface of the wafer. The ICC is configured to transform a small portion of copper film on the surface of the wafer into a water soluble form. The wafer surface is scrubbed. The wafer is then rinsed with a liquid. The rinsing is configured to remove the water soluble copper from the surface of the wafer and the brush, wherein the applying, the scrubbing, and the rinsing can be performed in a brush box or any other brush cleaning apparatus.
In another embodiment, a method is provided for removing surface materials from a wafer after a CMP operation. The wafer is scrubbed with an oxide etching chemical or HF to etch a small amount of silicon dioxide. The wafer is then scrubbed with deionized (DI) water to rinse the oxide etching chemical and/or HF. Next, the wafer is scrubbed with an improved cleaning chemical (ICC) after the scrubbing with the DI water. The wafer is then scrubbed with DI water after the scrubbing with the ICC.
In yet another embodiment, a method of treating a surface of a substrate is disclosed. The method includes: (a) transforming a copper film on the surface of the substrate into a water soluble form; (b) scrubbing the surface of the substrate with a brush; and (c) rinsing the substrate with a liquid, the rinsing being configured to remove post-CMP residues, the ICC, and the water soluble copper from the surface of the substrate and the brush.
Advantageously, the present invention provides a method for cleaning and treating a semiconductor wafer after a CMP operation. The method includes operations for cleaning embedded and left-over copper (Cu) material from a CMP operation. As discussed in the background, left-over copper may cause a decrease in adhesive strength of bonds between metallization features and conductive vias. The methods of the present invention provide techniques for treating the wafer surface so that conductive vias can bond better and stronger with underlying copper lines. A better, stronger bond also provides lower resistive links between copper lines of different layers.
Another advantage of the present invention is the removal of surface corrosion of the copper lines. As the ICC cleans the wafer surface, it also removes unwanted corroded copper. Still another advantage is the prevention of future corrosion of copper lines. By providing a layer of copper oxide over copper features, the method protects the copper features from future corrosion. Note that copper oxide (CuOx) is far less susceptible to corrosion than pure copper (Cu) lines. Additionally, the brush life can be extended since the cleaning techniques, and particularly the use of the ICC, also remove copper and other residues from the brushes during normal cleaning, treating, or etching. Ultimately, the methods disclosed herein will substantially reduce undue costs in the overall fabrication process because the number of damaged wafers that must be discarded will be substantially reduced.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.